As bandwidth demands for future generations of dynamic data rate (DDR) memory and peripheral component interconnect express (PCIe) technology increase, improved design of the individual components of input/output (I/O) channels to meet the desired electrical performance specifications is required. A socket that interconnects a microelectronic package to a motherboard, for example, may significantly contribute to channel loss and cross talk, thereby limiting channel margin at higher speeds. Thus, improving socket design enables interconnect technology for future high speed DDR and PCIe links.